There are two categories of silver and tin alloys. One is silver based or silver rich silver/tin alloys where the silver content is above 50%. Such alloys posses higher hardness and higher wear resistance compared to pure silver and are used in decorative applications. Due to their excellent electrical conductivity they may also be used in electronic connectors to reduce the amount of hard gold. Hard gold is used in electronic connectors as a contact material finish because it has good wear and corrosion resistance. The hard gold provides a low electrical contact resistance required for charge transport; however, the price of gold has been increasing such that it has become a limiting factor for low cost contact finishes. Silver/tin alloys have been used for connector finishes to replace or reduce the amount of hard gold. Such alloys have been produced by plating one or more alternating layers of silver and tin followed by diffusion in a non-oxidizing atmosphere to form the silver/tin alloy. U.S. Pat. No. 5,438,175 discloses an electronic connector having silver/tin as well as silver/palladium flash layers to enable a thin gold finish layer to produce a lower cost article.
The second type of alloy is the tin based alloys where silver content is near eutectic such as around 3.5%. The tin/silver alloy is a softer alloy than the silver/tin alloy and has hardness similar to pure tin. Such alloys may be used as low whiskering, lead-free solders. Of the various electronic applications for tin/silver alloys, there is a current focus in the semiconductor manufacturing industry on wafer-level-packaging (WLP). With wafer-level-packaging, IC interconnects are fabricated en masse on the wafer, and complete IC modules can be built on the wafer before it is diced. Benefits gained using WLP include, for example, increased I/O density, improved operating speeds, enhanced power density and thermal management, and decreased package size.
One of the keys to WLP is the build up of flip-chip conductive interconnect bumps on the wafer. These interconnect bumps serve as electrical and physical connections of the semiconductor components to a printed wiring board. Several methods of forming interconnect bumps on semiconductor devices have been proposed, for example, solder plate bumping, evaporation bumping, conductive adhesive bonding, stencil printing solder bumping, stud bumping, and ball placement bumping. Of these techniques, it is believed that the most cost effective technique for forming fine pitch arrays is solder plate bumping, which involves a combination of a temporary photoresist plating mask and electroplating. This technique is being rapidly adopted as full-area interconnect bump technology for high value-added assemblies such as microprocessors, digital signal processors, and application specific integrated circuits.
Typically tin/lead alloys are used in the formation of solder bumps; however, due to the toxicity of lead the industry has been trying to find acceptable lead-free tin alloys which can be readily co-deposited. Difficulties associated with co-deposition of lead-free tin alloys by electroplating arise when the materials being deposited have significantly different deposition potentials. Complications can arise, for example, when attempting to deposit alloys of tin (−0.137 V) with silver (0.799 V). The industry desires that the composition of the deposits be effectively controlled to prevent melting of the material at too high or too low a temperature for a given application. Poor compositional control can result in either a temperature too high for the components being treated to withstand or, on the other extreme, incomplete formation of the solder joint.
Another problem frequently encountered in electroplating bumps is bump morphology. For example, tin/silver bumps are electrodeposited through photoresist defined vias onto a copper or nickel under bump metal. The photoresist is stripped and the tin/silver is reflowed to form spherical bumps. Uniformity of bump size is important such that all of the bumps make contact with their electrical connections on a corresponding flip-chip component. In addition to bump size uniformity, it is important that a low density and volume of voids are formed during bump reflow. Ideally, no voids are formed during reflow. Voids in the bumps may also lead to interconnection reliability issues when joined to their corresponding flip-chip component. Another problem associated with plating bumps is the formation of nodules on the bump surface which are readily detectable with many conventional scanning electron microscopes. Such nodules may cause reflow voiding, and appearance wise deposits with nodules are not commercially acceptable.
Accordingly, there is a need for stable silver and tin alloy electroplating baths which can provide silver rich silver/tin alloys to replace hard gold and can provide tin rich tin/silver alloys to provide substantially nodule-free and void-free solder bumps.